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GS1528A / GS9068A HD-LINX(R) II Multi-Rate Dual Slew-Rate Cable Driver
GS1528A / GS9068A Data Sheet Features GS1528A * * * * * * * * SMPTE 292M, SMPTE 344M and SMPTE 259M compliant Dual coaxial cable driving outputs with selectable slew rate 50 differential PECL input Pb-free and RoHS compliant Pin compatible with GS9068A HD-LINX II SD SDI cable driver Seamless interface to other HD-LINX II family products Single 3.3V power supply operation Operating temperature range: 0C to 70C Description The GS1528A/9068A is a second generation high-speed BiCMOS integrated circuit designed to drive one or two 75 co-axial cables. The GS1528A may drive data rates up to 1.485Gb/s and provides two selectable slew rates in order to achieve compliance to SMPTE 259M, SMPTE 344M and SMPTE 292M. The GS9068A may drive data rates up to 540Mb/s and will achieve compliance to SMPTE 259M and SMPTE 344M. The GS1528A/9068A accepts a LVPECL level differential input that may be AC coupled. External biasing resistors at the inputs are not required. Power consumption is typically 168mW using a 3.3V power supply. The GS1528A/9068A is Pb-free, and the encapsulation compound does not contain halogenated flame retardant. This component and all homogeneous subcomponents are RoHS compliant.
GS9068A * * * * * * * * SMPTE 259M and SMPTE 344M compliant Dual coaxial cable driving outputs 50 differential PECL input Pb-free and RoHS compliant Pin compatible with GS1528A HD-LINX II multirate SDI dual slew-rate cable driver Seamless interface to other HD-LINX II family products Single 3.3V power supply operation Operating temperature range: 0C to 70C
Applications GS1528A * SMPTE 292M, SMPTE 344M and SMPTE 259M Coaxial Cable Serial Digital Interfaces.
GS9068A * SMPTE 259M and SMPTE 344M Coaxial Cable Serial Digital Interfaces.
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GS1528A / GS9068A Data Sheet
BANDGAP REFERENCE AND BIASING CIRCUIT
RSET
SDI SDI
INPUT DIFFERENTIAL PAIR
SDO OUTPUT STAGE & CONTROL SDO
SD/HD
GS1528A Functional Block Diagram
BANDGAP REFERENCE AND BIASING CIRCUIT
RSET
SDI SDI
INPUT DIFFERENTIAL PAIR
SDO OUTPUT STAGE & CONTROL SDO
GS9068A Functional Block Diagram
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GS1528A / GS9068A Data Sheet
Contents
Features ........................................................................................................................1 Applications...................................................................................................................1 Description ....................................................................................................................1 1. Pin Out ......................................................................................................................4 1.1 GS1528A Pin Assignment ..............................................................................4 1.2 GS9068A Pin Assignment ..............................................................................4 1.3 GS1528A / GS9068A Pin Descriptions ...........................................................4 2. Electrical Characteristics ...........................................................................................5 2.1 Absolute Maximum Ratings ............................................................................5 2.2 DC Electrical Characteristics ..........................................................................5 2.3 AC Electrical Characteristics ...........................................................................6 3. Solder Reflow Profiles ...............................................................................................7 4. Input / Output Circuits ...............................................................................................8 5. Detailed Description ..................................................................................................9 5.1 Input Interfacing ..............................................................................................9 5.2 Output Interfacing ...........................................................................................9 5.3 Output Return Loss Measurement ................................................................11 5.4 Output Amplitude Adjustment .......................................................................12 6. Application Information............................................................................................13 6.1 PCB Layout ...................................................................................................13 6.2 Typical Application Circuits ...........................................................................14 7. Package & Ordering Information .............................................................................15 7.1 Package Dimensions ....................................................................................15 7.2 Packaging Data .............................................................................................15 7.3 Ordering Information .....................................................................................15 8. Revision History ......................................................................................................16
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GS1528A / GS9068A Data Sheet
1. Pin Out
1.1 GS1528A Pin Assignment
SDI SDI VEE RSET 1 2 3 4 8 7 6 5 SDO SDO SD/HD VCC
GS1528A 8 PIN SOIC TOP VIEW
Figure 1-1: 8 Pin SOIC
1.2 GS9068A Pin Assignment
SDI SDI VEE RSET 1 2 3 4 8 7 6 5 SDO SDO NC VCC
GS9068A 8 PIN SOIC TOP VIEW
Figure 1-2: 8 Pin SOIC
1.3 GS1528A / GS9068A Pin Descriptions
Pin Number
1,2 3 4 5 6
Name
SDI, SDI VEE RSET VCC SD/HD
Timing
Analog - Analog - Non Synchronous
Type
Input Power Input Power Input
Description
Serial digital differential input. Most negative power supply connection. Connect to GND. External output amplitude control resistor. Most positive power supply connection. Connect to +3.3V. GS1528A: Output slew rate control. When set HIGH, the output will meet SMPTE 259M rise/fall time specifications. When set LOW, the serial outputs will meet SMPTE 292M rise/fall time specifications. GS9068A: No connect. Not connected internally. Serial digital differential output.
NC 7, 8 SDO, SDO
- Analog
- Output
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2. Electrical Characteristics
2.1 Absolute Maximum Ratings
Parameter
Supply Voltage Input ESD Voltage Storage Temperature Range Input Voltage Range (any input) Operating Temperature Range Solder Reflow Temperature Power Dissipation
Value
-0.5V to 3.6 VDC 2kV -50C < Ts < 125C -0.3 to (VCC +0.3)V 0C to 70C 260C 300mW
2.2 DC Electrical Characteristics
VDD = 3.3V, TA = 0C to 70C, unless otherwise shown
Parameter
Supply Voltage Power Consumption Supply Current Output Voltage Input Voltage SD/HD Input
Symbol
VCC PD Is VCMOUT VCMIN VIH VIL
Conditions
- TA = 25C TA = 25C Common mode Common mode - -
Min
3.135 - - - 1.6 + VSDI/2 2.4 -
Typ
3.3 168 51 VCC - VOUT - - - NOTES:
Max
3.465 - 64 - VCC - VSDI/2 - 0.8
Units
V mW mA V V V V
Notes
5% - - - - 1 1
Test Levels
3 5 1 6 6 7 7
TEST LEVELS 1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test.
1. This parameter applies only to the GS1528A.
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GS1528A / GS9068A Data Sheet
2.3 AC Electrical Characteristics
VDD = 3.3V, TA = 0C to 70C, unless otherwise shown
Parameter
Serial input data rate
Symbol
DRSDO DRSDO
Conditions
GS1528A GS9068A 1.485Gb/s 270Mb/s GS9068A SD/HD=0 SD/HD=1 GS9068A
Min
- - - - - - 400 400 - - - - - - - 15 750
Typ
- - 22 16 16 - - - - - - - - - - - 800
Max
1.485 540 - - - 220 800 800 30 30 100 100 10 8 8 - 850
Units
Gb/s Mb/s psp-p psp-p psp-p ps ps ps ps ps ps ps % % % dB mVp-p
Notes
1 - 2 - - 2, 3 2, 3 3 - 2 2 - 2 2 - - -
Test Levels
1 1 1 4 1 1 1 1 1 1 7 1 7 1 1 7 1
Additive jitter
- - -
Rise/Fall time
tr, tf tr, tf tr, tf
Mismatch in rise/fall time Duty cycle distortion - - - Overshoot - - - Output Return Loss Output Voltage Swing
tr,
tf
- SD/HD=0 SD/HD=1 GS9068A SD/HD=0 SD/HD=1 GS9068A - Single Ended into 75 external load RSET = 750
ORL VOUT
Input Voltage Swing TEST LEVELS
VSDI
Differential
300
- NOTES:
2000
mVp-p
-
7
1. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges. 2. Production test at room temperature and nominal supply voltage with guardbands for supply and temperature ranges using correlated test. 3. Production test at room temperature and nominal supply voltage. 4. QA sample test. 5. Calculated result based on Level 1, 2, or 3. 6. Not tested. Guaranteed by design simulations. 7. Not tested. Based on characterization of nominal parts. 8. Not tested. Based on existing design/characterization data of similar product. 9. Indirect test.
1. The input coupling capacitor must be set accordingly for lower data rates. 2. This parameter applies only to the GS1528A. 3. Rise/Fall time measured between 20% and 80%.
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GS1528A / GS9068A Data Sheet
3. Solder Reflow Profiles
The device is manufactured with Matte-Sn terminations and is compatible with both standard eutectic and Pb-free solder reflow profiles. MSL qualification was performed using the maximum Pb-free reflow profile shown in Figure 3-1. The recommended standard Pb reflow profile is shown in Figure 3-2.
Temperature 60-150 sec.
20-40 sec. 260C 250C 3C/sec max 217C 6C/sec max
200C
150C
25C
Time 60-180 sec. max 8 min. max
Figure 3-1: Maximum Pb-free Solder Reflow Profile (Preferred)
Temperature
60-150 sec.
10-20 sec. 230C 220C 3C/sec max 183C 6C/sec max 150C
100C
25C Time 120 sec. max 6 min. max
Figure 3-2: Standard Pb Reflow Profile (Pb-free package)
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GS1528A / GS9068A Data Sheet
4. Input / Output Circuits
VCC
SDI
SDI
VCC 10k 5k 10k
10k
Figure 4-1: Differential Input Stage (SDI/SDI)
Vcc
SDO SDO
IREF
Figure 4-2: Differential Output Stage (SDO/SDO) IREF derived using RSET
VCC
SD/HD
On Chip Reference
Figure 4-3: Slew Rate Select Input Stage (GS1528A only)
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5. Detailed Description
5.1 Input Interfacing
SDI/SDI are high impedance differential inputs. The equivalent input circuit is shown in Figure 4-1. Several conditions must be observed when interfacing to these inputs: * * * The differential input signal amplitude must be between 300 and 2000mVpp. The common mode voltage range must be as specified in the DC Electrical Characteristics table. For input trace lengths longer than approximately 1cm, the inputs should be terminated as shown in the Typical Application Circuit.
The GS1528A/9068A inputs are self-biased, allowing for simple AC coupling to the device. For serial digital video, a minimum capacitor value of 4.7F should be used to allow coupling of pathological test signals. A tantalum capacitor is recommended. SD/HD Input Pin (GS1528A only): The GS1528A SDO rise and fall times can be set to comply with both SMPTE 259M/344M and SMPTE 292M. For all SMPTE 259M standards, or any data rate that requires longer rise and fall time characteristics, the SD/HD pin must be set HIGH by the application layer. For SMPTE 292M standards and signals which require faster rise and fall times, this pin should be set LOW.
5.2 Output Interfacing
The GS1528A/9068A outputs are current mode, and will drive 800mV into a 75 load. These outputs are protected from accidental static damage with internal static protection diodes. The SMPTE 292M, SMPTE 344M and SMPTE 259M standards require that the output of a cable driver have a source impedance of 75 and a return loss of at least 15dB between 5MHz and 1.485GHz. In order for an SDI output circuit using the GS1528A/9068A to meet this specification, the output application circuit shown in Section 6.2 is recommended. The value of LCOMP will vary depending on the PCB layout, with a typical value of 5.6nH. A 4.7F capacitor is used for AC coupling the output of the device. This value is chosen to ensure that pathological signals can be coupled without a significant DC component occurring. Please see Section 6.0 for more details.
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GS1528A / GS9068A Data Sheet
Tek Stopped:
8110 Acquisitions
Figure 5-1: Output signal for 270Mb/s input
Tek Running: Normal
Figure 5-2: Output signal for 1.485Gb/s input (GS1528A only)
The output protection diodes act as a varactor (voltage controlled capacitor) as shown in Figure 5-3. Therefore, when measuring return loss at the GS1528A/9068A output, it is necessary to take the measurement for both a logic high and a logic low output condition. Consequently, the output capacitance of the device is dependent on the logic state of the output.
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GS1528A / GS9068A Data Sheet
GS1528A
SDO
SDO
Figure 5-3: Static Protection Diodes
5.3 Output Return Loss Measurement
To perform a practical return loss measurement, it is necessary to force the GS1528A/9068A output to a DC high or low condition. The actual measured return loss will be based on the outputs being static at VCC or VCC-1.6V. Under normal operating conditions the outputs of the device swing between VCC-0.4V and VCC-1.2V, so the measured value of return loss will not represent the actual operating return loss. A simple method of calculating the values of actual operating return loss is to interpolate the two return loss measurements. In this way, the values of return loss are estimated at VCC-0.4V and VCC-1.2V based on the measurements at VCC and VCC-1.6V. The two values of return loss (high and low) will typically differ by several decibels. If the measured return loss is RH for logic high and RL for logic low, then the two values can be interpolated as follows: RIH = RH- (RH-RL)/4 and RIL = RL+(RH-RL)/4 where RIH is the interpolated logic high value and RIL is the interpolated logic low value. For example, if RH = -18dB and RL = -14dB, then the interpolated values are RIH = -17dB and RIL = -15dB.
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GS1528A / GS9068A Data Sheet
5.4 Output Amplitude Adjustment
The output amplitude of the GS1528A/9068A can be adjusted by changing the value of the RSET resistor as shown in Table 5-1. For an 800mVp-p output with a nominal 7% tolerance, a value of 750 is required. A 1% SMT resistor should be used. The RSET resistor is part of the high speed output circuit of the GS1528A/9068A. The resistor should be placed as close as possible to the RSET pin. In addition, the PCB capacitance should be minimized at this node by removing the PCB groundplane beneath the RSET resistor and the RSET pin.
Table 5-1: RSET vs VOD RSET R ()
995 824 750 680 573
Output Swing (mVp-p)
608 734 800 884 1040
NOTE: For reliable operation of the GS1528A/9068A over the full temperature range, do not use an RSET value below 573.
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GS1528A / GS9068A Data Sheet
6. Application Information
6.1 PCB Layout
Special attention must be paid to component layout when designing serial digital interfaces for HDTV. An FR-4 dielectric can be used, however, controlled impedance transmission lines are required for PCB traces longer than approximately 1cm. Note the following PCB artwork features used to optimize performance: * * * * The PCB trace width for HD rate signals is closely matched to SMT component width to minimize reflections due to changes in trace impedance. The PCB groundplane is removed under the GS1528A/9068A output components to minimize parasitic capacitance. The PCB ground plane is removed under the GS1528A/9068A RSET pin and resistor to minimize parasitic capacitance. Input and output BNC connectors are surface mounted in-line to eliminate a transmission line stub caused by a BNC mounting via high speed traces which are curved to minimize impedance variations due to change of PCB trace width.
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GS1528A / GS9068A Data Sheet
6.2 Typical Application Circuits
* 5.6n 75 49.9 DIFFERENTIAL DATA INPUT 10n 49.9 1 2 3 GS1528A SDI SDI VEE RSET SDO SDO SD/HD VCC 8 7 6 75 75 75 * 5.6n BNC 4u7 VCC
BNC 4u7 10n
4u7
4u7
4 VCC
5
VCC 750 10n
* TYPICAL VALUE VARIES WITH LAYOUT
SD/HD NOTE: All resistors in Ohms, capacitors in Farads, and inductors in Henrys, unless otherwise noted.
Figure 6-1: GS1528A Typical Application Circuit
4u7 49.9 DIFFERENTIAL DATA INPUT 10n 49.9 1 2 3 GS9068A SDI SDI VEE SDO SDO NC 8 7 6
* 5.6n 75 75 75 75 * 5.6n VCC
BNC 4u7 10n
RSET
VCC
BNC 4u7
4u7
4 VCC
5
VCC 750 10n
* TYPICAL VALUE VARIES WITH LAYOUT
NOTE: All resistors in Ohms, capacitors in Farads, and inductors in Henrys, unless otherwise noted.
Figure 6-2: GS9068A Typical Application Circuit
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GS1528A / GS9068A Data Sheet
7. Package & Ordering Information
7.1 Package Dimensions
5.00 MAX. 0.49 MAX 1.91 MAX 1.27 MAX
8
5 0.25 4.0 MAX 6.20 MAX MAX
1
4 0.25 MAX = = =
0.60 MAX
3.81 0.05 3 spaces @ 1.27 0.05 8-pin SOIC All dimensions are in millimetres
7.2 Packaging Data
Parameter
Package Type Moisture Sensitivity Level Junction to Case Thermal Resistance, j-c Junction to Air Thermal Resistance, j-a (at zero airflow) Pb-free and RoHS Compliant
Value
8-pin SOIC 2 72C/W 116C/W Yes
7.3 Ordering Information
Part Number
GS1528A GS9068A GS1528ACKAE3 GS9068ACKAE3
Package
8-pin SOIC 8-pin SOIC
Temperature Range
0C to 70C 0C to 70C
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GS1528A / GS9068A Data Sheet
8. Revision History
Version
0 1
ECR
132954 133654
PCN
- -
Date
February 2004 June 2004
Changes and/or Modifications
New document. Modified AC Electrical Characteristics. Added reflow profiles. Upgraded from a preliminary data sheet to a data sheet. Updated to current document template to remove "Proprietary and Confidential" footer. Re-ordered solder reflow profiles to show preference for Pb-free profile. Clarified naming of standard Pb solder reflow profile. Added packaging data section. Updated document to reflect the RoHS compliance of both the GS1528A and GS9068A. Corrected process to BiCMOS. Corrected Input Differential Swing to 2200mV.
2
137403
-
July 2005
3 4
137886 139112
- 38124
September 2005 January 2006
CAUTION
ELECTROSTATIC SENSITIVE DEVICES DO NOT OPEN PACKAGES OR HANDLE EXCEPT AT A STATIC-FREE WORKSTATION DOCUMENT IDENTIFICATION
DATA SHEET
The product is in production. Gennum reserves the right to make changes to the product at any time without notice to improve reliability, function or design, in order to provide the best product possible.
GENNUM CORPORATION
Mailing Address: P.O. Box 489, Stn. A, Burlington, Ontario, Canada L7R 3Y3 Shipping Address: 970 Fraser Drive, Burlington, Ontario, Canada L7L 5P5 Tel. +1 (905) 632-2996 Fax. +1 (905) 632-5946
GENNUM JAPAN CORPORATION
Shinjuku Green Tower Building 27F, 6-14-1, Nishi Shinjuku, Shinjuku-ku, Tokyo, 160-0023 Japan Tel. +81 (03) 3349-5501, Fax. +81 (03) 3349-5505
GENNUM UK LIMITED
25 Long Garden Walk, Farnham, Surrey, England GU9 7HX Tel. +44 (0)1252 747 000 Fax +44 (0)1252 726 523 Gennum Corporation assumes no liability for any errors or omissions in this document, or for the use of the circuits or devices described herein. The sale of the circuit or device described herein does not imply any patent license, and Gennum makes no representation that the circuit or device is free from patent infringement. GENNUM and the G logo are registered trademarks of Gennum Corporation. (c) Copyright 2004 Gennum Corporation. All rights reserved. Printed in Canada. www.gennum.com
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